electric(1)

NAME

electric - a VLSI design system

SYNOPSIS

electric [-c] [-geom WxH+X+Y] [-i MACROFILE] [-m] [-n] [-t
technology] [library]

DESCRIPTION

Array-n requests that no session logging be done.

Array"schematic", "artwork", etc.

REPRESENTATION

Arrayangle. Arcs can also be stretchable or rigid under modification of their connecting nodes. These constraints propagate hierarchically from the bottom-up.

TECHNOLOGIES

ArrayIt has the universal arc and pin which can connect to ANY other
object and are therefore useful in mixed-technology designs. The
invisible arc can be used for constraining two nodes without making a connection. The unrouted arc can be used for electrical
connections that are to be routed later with real wires. The
facet-center primitive, when placed in a facet, defines the cursor origin on instances of that facet.

DESIGN-RULE CHECKING

Arrayto prepared for ECAD's Dracula design-rule checker.

COMPACTION

Arraywill compact in the vertical and horizontal directions until it
can find no way to compact the facet any further. It does not do
hierarchical compaction, does not guarantee optimal compaction,
nor can it handle non-manhattan geometry properly. The compactor
will also spread out the facet to guarantee no design-rule violations, if the "spread" option is set.

SIMULATION

Arraysource nodes. The source should then be parameterized to indicate the amount and whether it is voltage or current. For example, to make a 5 volt supply, create a source node and set the
SPICE fragment to: "DC 5". Next, exports must be created at all
inputs and they must be connected to the positive side of
sources. Next, all exports must be created at all points that
are being plotted and there must be meter nodes placed on them.
The node should have the top and bottom ports connected appropriately.

GENERATORS

Arrayreads a single personality table and generates the array and all
driving circuitry including power and ground connections. The
CMOS PLA generator reads two personality tables (AND and OR) and
also reads a library of PLA helper components (called "pla_mocmos") and generates the array.
A pad frame generator reads a disk file that describes the

pads, their placement, and their connection to a core facet.

ROUTING

Arraywill be stitched. Mimic stitching watches arcs that are created
by the user and adds similar ones at other places in the facet.

NETWORK COMPARISON

Arrayin one facet can be equated with nodes in the other. If the two
networks are automorphic or otherwise difficult to distinguish,
equivalence information can be specified prior to comparison by
selecting a component in the first facet then selecting a component in the second facet.

AUTHOR

ArrayRussell Wright (Queen's University): Lots of help
David J. Yurach (Queen's University): QUISC 2.0 Silicon

compiler

SEE ALSO

ArrayElectrical User's Guide.
Electric Internals manual.

FILES

Array*.spi SPICE simulation output
*.v VERILOG simulation output
*.ntk MOSSIM simulation output
*.sil SILOS simulation output
*.tdl TEXSIM simulation output
*.pal ABLE PAL simulation output

/usr/local/bin/spice Circuit level simulator: SPICE

11/12/00

electric(1)