Netlist::Cell(3pm)
NAME
Verilog::Netlist::Cell - Instantiated cell within a Verilog Netlist
SYNOPSIS
use Verilog::Netlist;
...
my $cell = $module->find_cell ('cellname');
print $cell->name;
DESCRIPTION
A Verilog::Netlist::Cell object is created by Verilog::Netlist for
every instantiation in the current module.
ACCESSORS
See also Verilog::Netlist::Subclass for additional accessors and
methods.
- $self->comment
- Returns any comments following the definition. keep_comments=>1
must be passed to Verilog::Netlist::new for comments to be
retained. - $self->delete
- Delete the cell from the module it's under.
- $self->gateprim
- True if the cell is a gate primitive instantiation (buf/cmos/etc), but not a UDP.
- $self->module
- Pointer to the module the cell is in.
- $self->name
- The instantiation name of the cell.
- $self->netlist
- Reference to the Verilog::Netlist the cell is under.
- $self->pins
- List of Verilog::Netlist::Pin connections for the cell.
- $self->pins_sorted
- List of name sorted Verilog::Netlist::Pin connections for the cell.
- $self->submod
- Reference to the Verilog::Netlist::Module the cell instantiates.
Only valid after the design is linked. - $self->submodname
- The module name the cell instantiates (under the cell).
MEMBER FUNCTIONS
See also Verilog::Netlist::Subclass for additional accessors and
methods.
- $self->lint
- Checks the cell for errors. Normally called by
Verilog::Netlist::lint. - $self->new_pin
- Creates a new Verilog::Netlist::Pin connection for this cell.
- $self->pins_sorted
- Returns all Verilog::Netlist::Pin connections for this cell.
- $self->dump
- Prints debugging information for this cell.
DISTRIBUTION
Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
software tool suite. The latest version is available from CPAN and
from <http://www.veripool.org/verilog-perl>.
Copyright 2000-2010 by Wilson Snyder. This package is free software;
you can redistribute it and/or modify it under the terms of either the
GNU Lesser General Public License Version 3 or the Perl Artistic
License Version 2.0.
AUTHORS
Wilson Snyder <wsnyder@wsnyder.org>
SEE ALSO
- Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist