Verilog-Perl(3pm)

NAME

Verilog-Perl - Overview of Verilog language packages for Perl

DESCRIPTION

The Verilog-Perl distribution provides Perl parsing and utilities for
the Verilog Language. This file provides an overview of the
distribution, for specific details on each component, see that
component's manpage.

You may also want to try the AUTO features present in
<http://www.veripool.org/verilog-mode> Verilog-Mode.

INSTALLATION

Skip this section if Verilog-Perl has already been installed.
Supported Systems: Verilog-Perl should run on any system with Perl, G++, Flex, and Bison. It is known to work on at least:; o sparc-sun-solaris2.5.1; o i386-linux; o i686-w2k-cygwin
CPAN Installation: Easiest installation is using the "CPAN" command line that comes
with Perl. After configuring CPAN the first time, simply

$ cpan
cpan> install Verilog-Perl; Read the rest of this file for details on the programs provided.
Manual Installation: Download the latest version from <http://www.perl.org/CPAN/>, or
from <http://www.veripool.org/verilog-perl>.; "cd" to the directory containing this README notice.; Type "perl Makefile.PL" to configure Verilog for your system.; Type "make" to compile Verilog. Some Solaris users have had
trouble with "open" being redefined. If this happens, try editing the Makefile to change _FILE_OFFSET_BITS to 32 instead of 64.; Type "make test" to check the package. If you don't have Synopsys' VCS, the test will print a warning, which you can ignore.; Type "make install" to install the programs and any data files and documentation.; Read the rest of this file for details on the programs provided.

SCRIPTS

The following scripts are installed by Verilog-Perl:

vhier: Vhier reads the Verilog files passed on the command line and
outputs a tree of all of the filenames, modules, and cells
referenced by that file.
vpassert: Vpassert will read the specified Verilog files and preprocess
special PLI assertions.
vppreproc: Vppreproc (Verilog-Perl Pre Processor) reads the Verilog files
passed on the command line and outputs preprocessed output.
vrename: Vrename will allow a signal to be changed across all levels of the design hierarchy, or to create a cross reference of signal names.

PACKAGES

Verilog::Getopt: Verilog::Getopt provides standardized handling of options similar
to Verilog/VCS and cc/GCC.
Verilog::Language: Verilog::Language provides general utilities for using the Verilog Language, such as parsing numbers or determining what keywords
exist.
Verilog::Netlist: Verilog::Netlist reads and holds interconnect information about a
whole design database.
Verilog::Netlist::Cell: A Verilog::Netlist::Cell object is created by Verilog::Netlist for every instantiation in the current module.
Verilog::Netlist::ContAssign: A Verilog::Netlist::ContAssign object is created by
Verilog::Netlist for every continuous assignment in the current
module.
Verilog::Netlist::File: Verilog::Netlist::File allows Verilog::Netlist objects to be read
and written in Verilog format.
Verilog::Netlist::Module: A Verilog::Netlist::Module object is created by Verilog::Netlist
for every module in the design.
Verilog::Netlist::Net: A Verilog::Netlist::Net object is created by
Verilog::Netlist::Module for every signal and input/output
declaration in the current module.
Verilog::Netlist::Pin: A Verilog::Netlist::Pin object is created by Verilog::Netlist::Cell for for each pin connection on a cell.
Verilog::Netlist::Port: A Verilog::Netlist::Port object is created by
Verilog::Netlist::Module for every port connection in the module.
Verilog::Netlist::Subclas: The Verilog::Netlist::Subclass is used as a base class for all
Verilog::Netlist::* structures.
Verilog::Parser: Verilog::Parser will tokenize a Verilog file and invoke various
callback methods.
Verilog::Preproc: Verilog::Preproc reads Verilog files, and preprocesses them
according to the Verilog specification. Programs can be easily
converted from reading a IO::File into reading preprocessed output from Verilog::Preproc.
Verilog::SigParse: Verilog::SigParser builds upon the Verilog::Parser package to
provide callbacks for when a signal is declared, a module
instantiated, or a module defined.

WHICH PARSER PACKAGE?

If you are starting a new application which needs to parse the Verilog language you have several tools available to you. Which you pick
depends on how low level and complete the information you need is.

VParseBison.y: The low level VParse* source files may be of use when you need a
starting point for your own a full C++ SystemVerilog grammar
parser, using Bison and Flex. It understands the full
SystemVerilog 2009 grammar (1800-2009 Appendix A).
Verilog::Preproc: Verilog::Preproc is useful when you need only text out, or a list
of defines, etc. It can preprocess a file, or be used to provide
the Verilog macro language on top of synthesis scripts. It
understands the full SystemVerilog 2009 preprocessor syntax.
Verilog::Parser: Verilog::Parser is useful when you need to tokenize or write source filters (where you need everything including whitespace). It can
take raw files, or preprocessed input. It understands all
SystemVerilog 2005 keywords.
Abstract Syntax Tree: Verilog::Parser knows enough to make a complete Abstract Syntax
Tree (AST) of Verilog syntax, however this hasn't been implemented yet. This would allow any arbitrary transformation of Verilog
syntax (everthing is known excluding whitespace). If you'd find
this useful please contact the author.
Verilog::SigParser: Verilog::SigParser is useful when you need a list of modules,
signals, ports, functions, etc. It requires a preprocessed file,
and can parse all SystemVerilog 2005 files, but only provides
callbacks on certain interesting things.
Verilog::Netlist: Verilog::Netlist is useful for when you need the hierarchy, and a
list of signals per module, pins per cell, etc. It builds upon the output of Verilog::SigParser, so requires preprocessed files. It
parses all SystemVerilog 2005 files, but not all SystemVerilog
constructs are loaded into objects.; This is probably the most popular choice.
VPI Using the VPI is the best way to access the behavior of the design.: It is not part of this package as it requires a compliant simulator and C++ code to call the VPI, and understands as much of the
language as the simulator supports. This allows writing lint
checks and full knowledge of all parts of the code, but generally
requires the most work (short of writing a parser from scratch.)
Verilator: The Verilator program also contains a very similar front end as
Verilog-Perl. It also understands how to elaborate and connect
complex pins and types. If you're looking to add some lint like
checks against netlists, this may be a better starting point.
Verilog-Mode for Emacs: Although not a parser, a common requested use of Verilog-Perl is to automatically make shell modules and interconnect modules.
Verilog-Mode is a better solution to this problem, as it results in completely portable code; the program (Verilog-Mode) isn't needed
for others to update the design. It's also in very common usage,
including by many IP providers.

FAQ

Why do I get "unexpected `do'" or "unexpected `bit'" errors?: Do, bit, ref, return, and other words are now SystemVerilog
keywords. You should change your code to not use them to insure it works with newer tools. Alternatively, surround them by the
Verilog 2005/SystemVerilog begin_keywords pragma to indicate
Verilog 2001 code.

`begin_keywords "1364-2001"
integer bit; initial bit = 1;

`end_keywords; Alternatively use the --language (for vhier) or
Verilog::Language::language_standard call to specify "1364-2001",
or for really old code, "1364-1995".; But, again, you really should fix the Verilog code.

DISTRIBUTION

Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and
from <http://www.veripool.org/verilog-perl>.

Copyright 2000-2010 by Wilson Snyder. This package is free software;
you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic
License Version 2.0.

This code is provided with no warranty of any kind, and is used
entirely at your own risk.

AUTHORS

Wilson Snyder <wsnyder@wsnyder.org>

docs.sk

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